#ALTERA QUARTUS II V13.0 SOFTWARE#
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#ALTERA QUARTUS II V13.0 FREE#
New features include additional math.h functions with enhanced precision and rounding parameterization, parameterizable FFT blocks for fixed- and floating-point FFTs, more efficient folding capability and improved resource sharing.įor additional information about the features offered in Quartus II software v13.0, visit Altera's What's New in Quartus II Software web page.īoth the Subscription Edition and the free Web Edition of Quartus II software v13.0 are now available for download. Further, these interfaces comply with ARM's TrustZone® requirements, allowing customers to partition an entire SoC-FPGA-based system between a secure world for critical system resources and a non-secure world for everything else.ĭSP Builder design tool enables system developers to effectively implement high-performance fixed- and floating-point algorithms into their DSP designs. Now Qsys can generate industry-standard AMBA® AHB and APB bus interfaces in the FPGA fabric. Qsys system integration tool provides expanded support for ARM®-based Cyclone® V SoCs. See today's press release for more information on the SDK for OpenCL and for more information on Altera's newly announced Preferred Board Partner Program for OpenCL. Software programmers targeting FPGAs achieve higher performance at significantly lower power compared to alternative hardware architectures. The OpenCL parallel programming model delivers the fastest path from code-to-hardware implementation. SDK for OpenCL opens the world of massively-parallel FPGA-based accelerators to software programmers without FPGA experience. The release also includes enhancements to the development suite's high-level C-based, system-/IP-based, and model-based design flows: Quartus II software v13.0 enables designs targeting Stratix V FPGAs to achieve the fastest Fmax of any FPGA in the industry with a two speed-grade advantage over the nearest competitor.
The most difficult-to-close designs targeting high-end 28 nm Stratix® V FPGAs will see compilation times slashed by 50 percent on average compared to the previous software release.
Users targeting 28 nm FPGAs and SoCs will experience on average a 25 percent reduction in compile times. San Jose, Calif., May 6, 2013- Altera Corporation (NASDAQ: ALTR) today announced the release of its Quartus® II software version 13.0, which delivers the highest levels of FPGA and SoC performance and designer productivity. Delivers Industry's Highest Performance Designs in Half the Time Compared to Previous Release